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KM681000B Family
Document Title
128K x8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 Initial draft for commercial product - Commercial Product only - Initial draft for Extended/Industrial Product - Datasheet for Extended/Industrial Product Finalized - Commercial product finalized at 1993 - Extended and industrial product finalized at 1994
Draft Data
October 28, 1992
Remark
Preliminary
0.1
September 1, 1993
Preliminary
1.0
September 1, 1993 September 24, 1994
Final
2.0
Revised April 12, 1996 - Change datasheet format : one datasheet for commercial, extended industrial product Revised - Change datasheet format - Erase 100ns part from extended and industrial product - Erase Low power part from TSOP package January 20, 1998
Final
3.0
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 3.0 January 1998
KM681000B Family
128K x8 bit Low Power CMOS Static RAM
FEATURES
* Process Technology : Poly Load * Organization : 128Kx8 * Power Supply Voltage : 4.5~5.5V * Low Data Retention Voltage : 2V(Min) * Three state output and TTL Compatible * Package Type : 32-DIP-600, 32-SOP-525 32-TSOP1-0820F/R
CMOS SRAM
GENERAL DESCRIPTION
The KM681000B families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Vcc Range Speed(ns) Standby (ISB1, Max) 100A 20A Extended(-25~85C) 4.5 to 5.5V 70 100A 50A Industrial(-40~85C) 70 100A 50A 70mA Operating (ICC2, Max) PKG Type
KM681000BL KM681000BL-L KM681000BLE KM681000BLE-L KM681000BLI KM681000BLI-L
Commercial(0~70C)
55/70
32-DIP,32-SOP 32-TSOP1 R/F 32-SOP 32-TSOP1 R/F 32-SOP 32-TSOP1 R/F
PIN DESCRIPTION
A11 A9 A8 A13 WE CS2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
N.C A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27
VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4
32-TSOP Type1 - Forward
A4 A5 A6 A7 A12 A13
32-DIP 32-SOP
26 25 24 23 22 21 20 19 18 17
Row select
Memory array 512 rows 256x8 columns
A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CS2 WE A13 A8 A9 A11
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
32-TSOP Type1-Reverse
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS1 A10 OE
A14 A15 A16
I/O1 I/O8
Data cont
I/O Circuit Column select
Data cont
Name
CS1,CS2 OE WE A0~A16 I/O1~I/O8 Vcc Vss N.C
Function
Chip Select Inputs Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs Power Ground No Connection
CS1 CS2 WE OE A0 A1 A2 A3 A8 A9 A10 A11
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 3.0 January 1998
KM681000B Family
PRODUCT LIST
Commercial Temperature Products (0~70C) Part Name
KM681000BLP-5 KM681000BLP-5L KM681000BLP-7 KM681000BLP-7L KM681000BLG-5 KM681000BLG-5L KM681000BLG-7 KM681000BLG-7L KM681000BLT-5L KM681000BLT-7L KM681000BLR-5L KM681000BLR-7L
CMOS SRAM
Extended Temperature Products (-25~85C) Part Name
KM681000BLGE-7 KM681000BLGE-7L KM681000BLTE-7L KM681000BLRE-7L
Industrial Temperature Products (-40~85C) Part Name
KM681000BLGI-7L KM681000BLTI-7L KM681000BLRI-7L
Function
32-DIP,55ns,L-pwr 32-DIP,55ns,LL-pwr 32-DIP,70ns,L-pwr 32-DIP,70ns,LL-pwr 32-SOP,55ns,L-pwr 32-SOP,55ns,LL-pwr 32-SOP,70ns,L-pwr 32-SOP,70ns,LL-pwr 32-TSOP F,55ns,LL-pwr 32-TSOP F,70ns,LL-pwr 32-TSOP R,55ns,LL-pwr 32-TSOP R,70ns,LL-pwr
Function
32-SOP,70ns,L-pwr 32-SOP,70ns,LL-pwr 32-TSOP F,70ns,LL-pwr 32-TSOP R,70ns,LL-pwr
Function
32-SOP,70ns,LL-pwr 32-TSOP F,70ns,LL-pwr 32-TSOP R,70ns,LL-pwr
Note : LL means Low Low standby current.
FUNCTIONAL DESCRIPTION
CS1 H X1) L L L CS2 X1) L H H H OE X1) X1) H L X1) WE X1) X1) H H L I/O Pin High-Z High-Z High-Z Dout Din Mode Deselected Deselected Output Disabled Read Write Power Standby Standby Active Active Active
1. X means dont care.( Must be low or high state.)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -25 to 85 -40 to 85 Soldering temperature and time TSOLDER 260C, 10sec (Lead Only) Unit V V W C C C C Remark KM681000BL KM681000BLE KM681000BLI -
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 3.0 January 1998
KM681000B Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.53) Typ 5.0 0 -
CMOS SRAM
Max 5.5 0 Vcc+0.52) 0.8 Unit V V V V
Note 1. Commercial Product : TA=0 to 70C, unless otherwise specified Extended Product : TA=-25 to 85C, unless otherwise specified Industrial Product : TA=-40 to 85C, unless otherwise specified 2. Overshoot : Vcc+3.0V in case of pulse width30ns 3. Undershoot : -3.0V in case of pulse width30ns 4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance Symbol CIN CIO Test Condition VIN=0V VIO=0V Min Max 6 8 Unit pF pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply Average operating current Output low voltage Output high voltage Standby Current(TTL) Symbol ILI ILO ICC ICC1 ICC2 VOL VOH ISB VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc CS1=VIL, CS2=VIH, IIO=0mA, VIN= VIL or VIH
Cycle time=1s, 100% duty, IIO=0mA, CS10.2V, CS2Vcc-0.2V, VIN0.2V or VINVcc-0.2V
Test Conditions
Min -1 -1 2.4 KM681000BL KM681000BL-L -
Typ Max Unit 7 1 1 15
1)
A A mA mA mA V V mA A A A
102) 70 0.4 3 100 20 100 50 100 50
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH
IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL, Other input=VIL or VIH
Standby Current(CMOS)
ISB1
CS1Vcc-0.2V, CS2Vcc-0.2V or CS20.2V Other input=0~Vcc
KM681000BLE KM681000BLE-L KM681000BLI KM681000BLI-L
1. 20mA for Exteneded and Industrial Products 2. 15mA for Extended and Industrial Products
Revision 3.0 January 1998
KM681000B Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, KM681000B Family : TA=0 to 70C, KM681000BE Family : TA=-25 to 85C,
KM681000BI Family : TA=-40 to 85C) Speed Bins Parameter List Symbol Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO1,tCO2, tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5 55ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 70ns Max 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Symbol VDR CS11)Vcc-0.2V KM681000BL KM681000BL-L Data retention current IDR Vcc=3.0V CS1Vcc-0.2V, CS2Vcc-0.2V or CS20.2V Other Input+0~Vcc KM681000BLE KM681000BLE-L KM681000BLI KM681000BLI-L Data retention set-up time Recovery time tRDR tRDR See data retention waveform Test Condition Min 2.0 0 5 Typ 1 0.5 Max 5.5 50 10 50 25 50 25 ms A Unit V
1. CS1VCC-0.2V,CS2VCC-0.2V(CS1 controlled) or CS20.2V(CS2 controlled)
Revision 3.0 January 1998
KM681000B Family
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH
OE tOLZ tLZ Data Valid tOHZ
Data out
NOTES (READ CYCLE)
High-Z
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
Revision 3.0 January 1998
KM681000B Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4)
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1
Controlled)
tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
Revision 3.0 January 1998
KM681000B Family
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC Address tAS(3) CS1 tAW CS2 tCW(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4)
CMOS SRAM
WE
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC 4.5V tSDR Data Retention Mode tRDR
2.2V VDR CS1VCC - 0.2V CS1 GND
CS2 controlled
VCC 4.5V CS2 tSDR
Data Retention Mode
tRDR
VDR CS20.2V 0.4V GND
Revision 3.0 January 1998
KM681000B Family
PACKAGE DIMENSIONS
32 DUAL INLINE PACKAGE (600mil)
CMOS SRAM
Units : millimeter(inch)
+0.10 -0.05 +0.004 0.010-0.002
0.25
#32
#17
13.600.20 0.5350.008
#1 42.31 1.666 MAX 4.1910.20 1.6500.008
#16 3.810.20 0.1500.008 5.08 0.200 MAX
15.24 0.600
0~15
( 1.91 ) 0.075
0.460.10 0.0180.004 1.520.10 0.0600.004
3.300.30 0.1300.012 2.54 0.100 0.38 0.015 MIN
32 PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8 #32 #17
14.120.30 0.5560.012
11.430.20 0.4500.008
#1 20.87 MAX 0.822 20.470.20 0.8060.008
#16 2.740.20 0.1080.008 3.00 0.118 MAX
13.34 0.525
0.20 +0.10 -0.05 0.008+0.004 -0.002
0.800.20 0.0310.008
0.10 MAX 0.004 MAX
+0.100 -0.050 +0.004 0.016 -0.002
( 0.71 ) 0.028
0.41
1.27 0.050
0.05 0.002 MIN
Revision 3.0 January 1998
KM681000B Family
PACKAGE DIMENSIONS
32 THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
0.20
+0.10 -0.05 0.008+0.004 -0.002
CMOS SRAM
Units : millimeter(inch)
20.000.20 0.7870.008 #32 ( 8.00 0.315 0.25 ) 0.010
#1
8.40 0.331 MAX
0.50 0.0197
#16
#17 1.000.10 0.0390.004 1.20 0.047 MAX
+0.10 -0.05 0.006+0.004 -0.002
0.05 0.002 MIN
0.25 0.010 TYP
18.400.10 0.7240.004
0.15
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
32 THIN SMALL OUTLINE PACKAGE TYPE I (0820R)
0.20
+0.10 -0.05
0.008+0.004 -0.002 #16
20.000.20 0.7870.008 #17 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010
0.50 0.0197
#1
#32 1.000.10 0.0390.004 1.20 0.047 MAX 0.05 0.002 MIN
0.25 0.010 TYP
18.400.10 0.7240.004
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
0.10 MAX 0.004 MAX
+0.10 -0.05 +0.004 0.006 -0.002
0.15
Revision 3.0 January 1998
0.004 MAX 1.10 MAX

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